Today large system-on-chips (SOC) are being designed that include a myriad of different types of complex functional circuits. Standardized IC test interfaces and architectures are needed for testing these functional circuits within the IC, and also for testing the board/substrate on which the IC will eventually reside.
This disclosure describes two separate IC test standards, IEEE 1149.1, adopted on Feb. 15, 1990, and IEEE P1500, provisional, that can be used to test circuitry embedded within ICs. Each IC test standard has its own test interface and architecture, and unique testing features. Thus an IC may require both test standards to be implemented to achieve an overall testing goal. Having to include both test standards in ICs can be costly in circuit area overhead and test complexity.
To facilitate the understanding of the present disclosure, an overview of two test standards to be combined is provided. FIGS. 1-17 give an overview of IEEE standard 1149.1 and FIGS. 18-45 give an overview of IEEE standard P1500.
IEEE 1149.1 Overview
FIG. 1 illustrates an example of a test interface 104 and architecture 102 that is commonly used in both ICs and core circuits within ICs. The test interface and architecture are well known and were standardized in 1990 as IEEE Standard 1149.1. While initially developed as an IC test standard for primarily supporting board level IC to IC interconnect testing, this standard has evolved into additional uses and formed the basis for a family of additional IEEE standards.
The test interface 104 includes a test access port (TAP) state machine controller and signals TDI, TCK, TMS, TRST, and TDO. The test architecture 102 includes an instruction register and a set of selectable data registers. As seen in FIG. 1, the data registers consists of various types including but not limited too, a boundary scan register, digital test registers, debug/emulation registers, programming registers, mixed signal test registers, and a bypass register. The TAP receives a test clock (TCK), test mode select (TMS), and test reset (TRST) input signals. The TAP responds to the TCK and TMS input signals to shift data through either the instruction register or a selected data register from the test data input (TDO) signal to the test data output (TDO) signal. The TAP has proven to be an efficient and popular test control interface for ICs and cores.
For example, other TAP based standards have evolved from the original IEEE 1149.1 standard. These other TAP based standards include; (1) IEEE standard 1149.4 (a mixed signal test standard), (2) IEEE standard 1149.6 (an advanced interconnect test standard), (3) IEEE standard 1532 (an in-system programming standard), and (4) IEEE standard 5000 (a debug/emulation standard). The naming of the data registers in FIG. 1 indicates the presence of these additional TAP based IEEE standards. In addition to the multiplicity of TAP based IEEE standards, numerous core and/or IC provider companies have developed proprietary emulation and debug architectures based upon the IEEE 1149.1 TAP and architecture of FIG. 1.
FIG. 2 is a different view of the FIG. 1 test interface and architecture emphasizing the instruction registers ability to select one of the data registers for access between TDI and TDO.
FIG. 3 is a block diagram of the key circuit elements of FIGS. 1 and 2. The TAP 318 regulates TDI to TDO access of the instruction register 314 via instruction register control bus 302 and the TDI to TDO access of a selected one of a set of data registers 316 via data register control bus 304. As seen, a gating circuit 308 receives input 306 from the instruction register to allow the data register control bus 304 from the TAP to pass through the gating circuit and be output on bus 310 to operate a selected data register. The gating circuit is typically viewed as being part of the instruction register and is shown in FIG. 2 as the dotted box on the instruction register. The data registers 316 also receive mode control input 312 from the instruction register to place them in various modes of operation.
FIG. 4 indicates the TAP's state controller diagram. The TAP is clocked, via TCK, through these states in response to input on TMS. Since all TAPs operate from this diagram, standardized plug and play compatibility between TAPs is guaranteed. The operation of the TAP controller is well known.
FIG. 5 illustrates typical TAP 318 input (TCK, TMS, TRST) and output signals. The ClockIR, ShiftIR, and UpdateIR form the signals on bus 302 to the instruction register. The ClockDR, ShiftDR, and UpdateDR form the signals on bus 304 to gating circuit 308. The Select signal is used to select either the instruction register or selected data register to be coupled to TDO. The Reset signal is used to reset the instruction register and optionally the data registers whenever the TAP is in the TRST state of FIG. 4. As seen in FIG. 5, a TAP state bus 502 can be output from the TAP to indicate what state of FIG. 4 the TAP is in. The TAP state bus is useful in controlling synchronous instruction and data register designs and is therefore shown as being part of the instruction and data control buses 302 and 304, respectively.
FIGS. 6, 6A and 6B illustrate a gated instruction register design style. The instruction register comprises a shift register 602, an update register 604, and an instruction decode logic 606. The shift register comprises serially connected scan cells 608 that operate to capture and shift data from TDI to TDO. The update register comprises a flip-flop or latch 610 for each shift register scan cell 608. In operation, the TAP outputs control (ClockIR and ShiftIR) to cause the shift register to capture data (IN) then shift data from TDI to TDO. After capturing and shifting, the TAP outputs control (UpdateIR) to cause the latches 610 of update register 604 to load data from the scan cells 608. The latched data is output from the update register to the decode logic, where it is decoded into control output bus 612 which, among other things, drives buses 306 and 312. While not shown, both the scan cell 608 and update latch 610 can be reset by the reset output from the TAP.
FIG. 7 illustrates a timing example of the TAP performing the above described gated instruction register scan operation. As seen, the TAP gates the ClockIR on in the CaptureIR state to perform the capture operation (C) and in the ShiftIR state to perform the shift operations (S). The TAP manipulates the ShiftIR output to control the scan cells 608 to perform the capture and shift operations. Also, the TAP gates a clock pulse on UpdateIR during the UpdateIR state to perform the update operation (U).
FIGS. 8, 8A, and 8B illustrate a synchronous instruction register design style. The synchronous instruction register design style differs from the gated instruction design style in that the shift register 802 is comprised of scan cells 804 which operate from the free running TCK input, not the ClockIR input of FIG. 6. The shift register 802 receives TAP state (502) input from bus 302 to indicate when the TAP is in the CaptureIR state and ShiftIR state. When the TAP is in the CaptureIR state the scan cells 804 capture data (IN) and when the TAP is in the ShiftIR state the scan cells shift data from TDI to TDO. When the TAP is not in the CaptureIR or ShiftIR state, the scan cells hold their present value. The operation of the update register 604 and decode logic 606 is the same as describe in FIG. 6.
FIG. 9 illustrates a timing example of the TAP performing the above described synchronous instruction register scan operation. As seen, when the TAP enters the CaptureIR state the scan cells 804 perform a capture operation (C) and when the TAP enters the ShiftIR state the scan cells perform shift operations (S). As with the FIG. 7 timing diagram, the TAP gates a clock pulse on UpdateIR during the UpdateIR state to perform the update operation (U).
FIGS. 10 and 10B illustrate a first gated data register design style. The data register 1002, referred to as data register 1, is an example of a gated boundary scan data register that could be used at the I/O boundary of a core or IC. Data register 1 comprises serially connected boundary scan cells 1004 each having an scan cell 1006 operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch 1008 operable to load data from the scan cell. If selected by the instruction in the instruction register, gates 1010-1012 within gating circuit 308 are enabled by a signal 1014 on bus 306 to couple the TAP's ClockDR, ShiftDR, and UpdateDR outputs to data register 1's Clock-1, Shift-1, and Update-1 inputs, respectively. This enables scan access of data register 1. In the figures of the provisional application from which priority is claimed, a capital “A” in a gate symbol indicates the gate is an AND function and a capital “O” in a gate symbol indicates the gate is an OR function. During a data scan operation, the TAP outputs control (ClockDR and ShiftDR) to cause the scan cells 1006 of boundary scan cells 1004 to capture data (IN) then shift data from TDI to TDO. After capturing and shifting, the TAP outputs control (UpdateDR) to cause the update latches 1008 of the boundary scan cells to load data from the scan cells 1006. If data register 1 is in test mode, the Mode-1 input from instruction register bus 312 will be set to cause the data in update latch 1008 to be output from data register 1002.
FIG. 11 illustrates a timing example of the TAP performing the above described gated data register scan operation. As seen, the TAP gates Clock-1 (ClockDR) on in the CaptureDR state to perform the capture operation (C) and in the ShiftDR state to perform the shift operations (S). The TAP manipulates Shift-1 (ShiftDR) to control the scan cells 1006 to perform capture and shift operations. Also, the TAP gates a clock pulse on UpdateDR-1 during the UpdateDR state to perform the update operation (U). It is important to note for later reference in this and following timing figures that the dotted box area beginning with A and ending with B indicates when the TAP is in the ShiftDR state.
FIGS. 12 and 12A illustrate a first synchronous data register design style. The data register 1202, referred to as data register 2, is an example of a synchronous boundary scan data register that could be used at the I/O boundary of a core or IC. Data register 2 comprises serially connected boundary scan cells 1204 each having an scan cell 1206 operable to capture data from the IN input and to shift data from TDI to TDO, and an update latch 1208 operable to load data from the scan cell. If selected by the instruction in the instruction register, gates 1210-1214 within gating circuit 308 will be enabled by a signal 1216 on bus 306 to couple the TAP's CaptureDR state, ShiftDR state, and UpdateDR outputs to data register 2's Capture-2, Shift-2, and Update-2 inputs, respectively. This enables scan access of data register 2. The Clock-2 input of data register 2 is coupled to the free running TCK. During a data scan operation, the TAP outputs state indications (bus 502 & 304) to cause the scan cells 1206 to capture data (IN) during the CaptureDR state (Capture-2 set high) then shift data from TDI to TDO during the ShiftDR state (Shift-2 set high). As seen, the scan cell holds its state when the TAP is not in the CaptureDR or ShiftDR states. After capturing and shifting, the TAP outputs control (UpdateDR) to cause the update latches 1208 of the boundary scan cells to load data from the scan cells 1206. If data register 2 is in test mode, the Mode-2 input from instruction register bus 312 will be set to cause the data in update latch 1208 to be output from data register 1202.
FIG. 13 illustrates a timing example of the TAP performing the above described synchronous data register scan operation. As seen, when the TAP is in the CaptureDR state, the Capture-2 input is high causing data register 2 to capture data (C). When the TAP is in the ShiftDR state the Shift-2 input is high causing data register 2 to shift data (S). Also, the TAP gates a clock pulse on UpdateDR-2 during the UpdateDR state to perform the update operation (U).
FIGS. 14 and 14A illustrate a second gated data register design style. The data register 1402, referred to as data register 3, is an example of a gated scan data register that could be used as an internal scan path of a core or IC. Data register 3 comprises serially connected conventional scan cells 1404 each operable to capture data from the IN input and to shift data from TDI to TDO. If selected by the instruction in the instruction register, multiplexers 1405-1407 within gating circuit 308 are enabled by a signal 1408 on bus 306 to couple the TAP's ClockDR and ShiftDR outputs to data register 3's Clock-3 and Shift-3 inputs, respectively. Multiplexers 1405-1407 are used instead of gates since switching between a functional and test clocks and between functional and test modes is required when using scan cells that are shared for functional and test operations. This enables scan access of data register 3. During a data scan operation, the TAP outputs control (ClockDR and ShiftDR) to cause the scan cells 1404 to capture data (IN) then shift data from TDI to TDO.
FIG. 15 illustrates a timing example of the TAP performing the above described gated data register scan operation. As seen, the TAP gates Clock-3 (ClockDR) on in the CaptureDR state to perform the capture operation (C) and in the ShiftDR state to perform the shift operations (S). The TAP manipulates Shift-3 (ShiftDR) to control the scan cells 1404 to perform capture and shift operations.
FIG. 16 illustrates a second synchronous data register design style. The data register 1602, referred to as data register 4, is an example of a synchronous scan data register that could be used as an internal scan path of a core or IC. Data register 4 comprises serially connected scan cells 1604 each operable to capture data from the IN input and to shift data from TDI to TDO. If selected by the instruction in the instruction register, multiplexers 1606-1610 within gating circuit 308 will be enabled by a signal 1612 on bus 306 to couple the TAP's CaptureDR state output, the TAP's ShiftDR state output, and the TCK to data register 4's Capture-4, Shift-4, and Clock-4 inputs, respectively. Again, multiplexers 1606-1610 are used instead of gates since switching between a functional and test clocks and between functional and test modes is required when using scan cells that are shared for functional and test operations. This enables scan access of data register 4. During a data scan operation, the TAP outputs state indications to cause the scan cells 1604 to capture data (IN) during the CaptureDR state (Capture-4 set high) then shift data from TDI to TDO during the ShiftDR state (Shift-4 set high). As seen, the scan cell holds its state when the TAP is not in the CaptureDR or ShiftDR states.
FIG. 17 illustrates a timing example of the TAP performing the above described synchronous data register scan operation. As seen, when the TAP is in the CaptureDR state, the Capture-4 input is high causing data register 4 to capture data (C). When the TAP is in the ShiftDR state the Shift-4 input is high causing data register 4 to shift data (S).
IEEE P1500 Overview
FIG. 18 illustrates an example of a test interface 1804 and architecture 1802 that is being developed as IEEE standard P1500. This standard test interface and architecture is being developed for the purpose of testing cores within ICs. While not yet standardized, the state of the P1500 standard is stable and near complete. The architectural similarities between the IEEE P1500 standard of FIG. 18 and the previously described IEEE 1149.1 standard of FIG. 1 are clearly seen.
The test interface 1804 includes a wrapper serial port (WSP) and signals WSI, Clock, Capture, Shift, Update, Transfer, Select, Reset, and WSO. The architecture 1802 includes a wrapper instruction register and a set of selectable wrapper data registers. As seen in FIG. 18, the wrapper data registers include wrapper boundary registers, digital test registers, and a wrapper bypass register. The WSP receives clock, capture, shift, update, transfer, select, and reset input signals. The WSP responds to these signals to shift data through either the wrapper instruction register or a selected wrapper data register from the wrapper serial input (WSI) signal to the wrapper serial output (WSO) signal. Unlike the TAP of FIG. 1, which is a state machine, the WSP is simply a combinational decode circuit. With the exception that IEEE standard P1500 uses a WSP in the test interface 1804 and IEEE standard 1149.1 uses a TAP in the test interface 104, the two standards are very similar architecturally. For the purpose of simplifying the following description, it will be assumed that the IEEE P1500 architecture 1802 can be viewed as being the same as the previously described IEEE 1149.1 architecture 102 of FIG. 1. While there may be subtle differences between the two architectures, these differences are transparent to the overall objective of the present disclosure.
FIG. 19 is a different view of the FIG. 18 test interface and architecture emphasizing the instruction registers ability to select one of the data registers for access between WSI and WSO.
FIG. 20 is a block diagram of the key circuit elements of FIGS. 18 and 19. The WSP 202 regulates WSI to WSO shifting of the instruction register 314 via instruction register control bus 302 and the WSI to WSO shifting of a selected data within a set of data registers 316 via data register control bus 304. As seen, a gating circuit 308 receives input 306 from the instruction register to allow the data register control bus 304 from the WSP to pass through the gating circuit and be output on bus 310 to operate the selected data register. The gating circuit is typically viewed as being part of the instruction register and is shown in FIG. 18 as the dotted box on the instruction register. The data registers 316 also receive mode control input 312 from the instruction register to place them in various modes of operation.
FIG. 21 illustrates an example WSP 202 circuit. As mentioned, the WSP is a combinational circuit and does not include any sequential memory elements. Like the TAP, the WSP has a control bus 302 of outputs, ClockIR, ShiftIR, CaptureIR, and UpdateIR, that are used to control scanning of the instruction register, and a control bus 304 of outputs, ClockDR, ShiftDR, CaptureDR, UpdateDR, and TransferDR, that are used to control scanning of a selected data register.
The operation of the WSP is simple. If the select input to the WSP is low the select output from the WSP is low and the WSP couples the clock, shift, capture, update, and transfer inputs to the ClockDR, ShiftDR, CaptureDR, UpdateDR, and TransferDR outputs to enable scanning of a data register. The low on the select output selects the data register between WSI and WSO. If the select input to the WSP is high the select output from the WSP is high and the WSP couples the clock, shift, capture, and update inputs to the ClockIR, ShiftIR, CaptureIR, and UpdateIR outputs to enable scanning of the instruction register. The high on the select output selects the instruction register between WSI and WSO. The reset output from the WSP is coupled to the reset input to the WSP and is used, as was the reset output of the TAP in FIG. 5, to reset the instruction register and optionally the data registers when asserted low. The WSP Transfer input and TransferDR output signals are new data register control signals introduced by IEEE P1500. An example of their use will be described later in regard to FIGS. 40-45.
FIGS. 22, 22A, 22B, and 23 are provided to illustrate that the WSP is capable of providing timing and control to the gated instruction register design of FIG. 6. FIG. 23 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 7. The dotted line clock pulses shown on portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the instruction register scan timing diagram of FIG. 7.
FIGS. 24, 24A, 24B, and 25 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous instruction register design of FIG. 8. FIG. 25 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 9. Being able to mimic TAP instructions and, as will be shown below, data register scan timing is important since it provides for serially connecting the IEEE 1149.1 and IEEE P1500 standard test architectures together in a daisy-chain arrangement.
FIGS. 26, 26A, and 27 are provided to illustrate that the WSP is capable of providing timing and control to the gated data register 1 design of FIG. 10. FIG. 27 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 11. Again, the dotted line clock pulses shown on portions of the inactive clock input signal indicates TCKs that would be input to the TAP during the data register scan timing diagram of FIG. 11.
FIG. 28 illustrates an alternate method of scanning gated data register 1 of FIG. 26. Since the WSP is combinational in operation it does not have to mimic TAP state transition timing. Indeed one of the primary reasons IEEE P1500 uses the WSP instead of the TAP is that the WSP provides greater flexibility in controlling scan operations. For example, in FIG. 28 the WSP provides scan timing control to data register 1 where the shift (S), capture (C), and update (U) operations are occurring in a tightly timed sequence.
FIGS. 29, 29A, and 30 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous data register 2 design of FIG. 12. FIG. 31 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 13.
FIG. 31 illustrates an alternate method of scanning synchronous data register 2 of FIG. 26, whereby the shift (S), capture (C), and update (U) operations are occurring in a tightly timed sequence.
FIGS. 32, 32A, and 33 are provided to illustrate that the WSP is capable of providing timing and control to the gated data register 3 design of FIG. 14. FIG. 33 illustrates that the WSP can mimic the gated TAP timing diagram of FIG. 15.
FIGS. 34 and 35 illustrate alternate methods of scanning gated data register 3 of FIG. 32. FIG. 34 illustrates a tightly timed capture (C) and shift (S) scanning sequence, and FIG. 35 illustrates a tightly timed back to back capture (C) and shift (S) sequence.
FIGS. 36, 36A, and 37 are provided to illustrate that the WSP is capable of providing timing and control to the synchronous data register 4 design of FIG. 16. FIG. 37 illustrates that the WSP can mimic the synchronous TAP timing diagram of FIG. 17.
FIGS. 38 and 39 illustrate alternate methods of scanning synchronous data register 4 of FIG. 36. FIG. 38 illustrates a tightly timed capture (C) and shift (S) scanning sequence, and FIG. 39 illustrates a tightly timed back to back capture (C) and shift (S) sequence.
FIGS. 40 and 40A illustrate one example of how the IEEE P1500 Transfer signal might be used during test. Data register 5, 4002, is comprised of a plurality of serially connected scan cells 4004, each capable of performing shift and transfer operations. As seen, the scan cell 4004 circuit example consists of an input multiplexer 4012, a series of flip flops 4014, and an output multiplexer 4016. The input multiplexer 4012 serves to either shift data from TDI (WSI) to TDO (WSO) in shift mode (Shift5 is high) or to shift in data from the output (OUT) of the output multiplexer 4016 during transfer mode (Transfer5 is high). Gates 4006 and 4008 of gating circuit 308 are enabled by signal 4010 to couple the ClockDR and TransferDR outputs from the WSP to the Clock-5 and Transfer-5 inputs to data register 5, respectively, when a transfer instruction is loaded into the instruction register.
A pair of Mode-5 signals, Mode-5a and 5b, are output from the instruction register on bus 312 to control the scan cell output multiplexers 4016. During transfer operations, the output multiplexers 4016 of scan cells 4004 that output test signals will be controlled to couple the output of the flip flops 4014 to the output multiplexer output (OUT), while the output multiplexers 4016 of scan cells 4004 that input test signals will be controlled to couple the input (IN) of the scan cell to the output (OUT) of output multiplexers 4016. Thus two separately controllable Mode-5 signals, Mode-5a and 5b, will typically be required from the instruction register to achieve a desired output multiplexer test setting.
FIG. 41 illustrates an example transfer test arrangement whereby an AND gate function 4102 to be tested is bounded by two cells A and B 4004 for providing input to the AND gate and one cell C 4004 for receiving output from the AND gate. The AND gate can exist within a core containing the IEEE P1500 architecture or external to a core containing the IEEE P1500 architecture. Also, the cells A-C may be in the same data register 5 of one IEEE P1500 architecture or be in separate data register 5's of separate IEEE P1500 architectures. The dotted line beginning at the TDI input of cell A and ending at the TDO output of cell C indicates the process of shifting data through the cells to load test input data to cells A and B and unload test output data from cell C. As seen, the shifting occurs in response to Shift-5 being high, Transfer-5 being low, and Clock-5 being active. While for simplicity the example of FIG. 41 shows the serial path to only include cells A-C, additional scan cells of various types may exist in the scan path as well.
FIG. 42 illustrates cells A, B, and C 4004 in their transfer mode. As seen, the transfer mode occurs in response to Shift-5 being low, Transfer-5 being high, and Clock-5 being active. During transfer mode, cells A and B circulate their data, as shown in dotted line, from the output (OUT) of their output multiplexers to the input of their input multiplexers, to provide the test signal input to AND gate 4102. Simultaneously, cell C shifts in the test signal output from AND gate 4102, again as shown in dotted line. The Mode-5a and Mode-5b inputs to the cell output multiplexers have been set, as previously described, for this particular transfer test arrangement.
FIG. 43 shows a first transfer test input and output session to AND gate function 4102. FIG. 44 shows a second transfer test input and output session to AND gate function 4102. The first transfer test session tests the AND gate's ability to pass a stream of data from its In1 input to its Out output, while its In2 input is high. The second transfer test session tests the AND gate's ability to pass a stream of data from its In2 input to its Out output, while its In1 input is high.
FIG. 45 illustrates an example timing diagram for the transfer test of the test arrangement of FIGS. 41-44. Firstly, the cells A-C are shifted, during time frame 4502, to load the test input patterns to be applied during the first transfer test session of FIG. 43. Secondly, the first transfer test session of FIG. 43 is executed during time frame 4504. Thirdly, the cells A-C are shifted, during time frame 4506 to load the test input patterns to be applied during the second transfer test session of FIG. 44 and to unload the results of the first transfer test session of FIG. 43. Fourthly, the second transfer session of FIG. 44 is executed during time frame 4508. Lastly, the cells A-C are shifted, during time frame 4510 to unload the test results of the second transfer test session.
While the above description has provided one detailed example of how an IEEE P1500 transfer test may be performed, there are numerous other ways of designing and operating scan cells to achieve transfer testing.
FIG. 46 represents the problems presented if both TAP based (i.e. IEEE 1149.1, 1149.4, 1149.6, 1532, 5000, and ad-hoc) and the WSP based (i.e. IEEE P1500) standard architectures (domains) are required in core and/or IC designs. In FIG. 46, box 4602 represents a circuit which can be either a core circuit for use in an IC or an entire IC. The circuit 4602 is shown including both TAP based standards (1149.1, 1149.4, 1149.6, 1532, 5000, and/or ad-hoc) and the WSP based standard (IEEE P1500).
As seen in FIG. 46, each of the TAP based standards included in circuit 4602 advantageously share a common TAP 318 interface and architecture 4604. The architecture 4604 includes a commonly shared instruction register 314, a commonly shared set of selectable data registers 316, commonly shared gating circuitry 308, and commonly shared instruction 302 and data 304 control buses to the commonly shared TAP 318. The external TAP test bus 4608 is achieved using 5 signals (TDI, TDO, TCK, TMS, and TRST). Regardless of whether circuit 4602 is a core or an IC, these 5 signals are dedicated and reserved for use in accessing the TAP to perform testing or other operations with the common architecture 4604. The availability of the dedicated TAP test bus has proven very beneficial since it provides non-intrusive access to a functionally operating circuit 4602 to perform real time test, emulation, debug, and other operations. The dedicated TAP test bus has also lead to an ever increasing set of TAP interface support tools supporting test, emulation, debug, programming, and other TAP based operations.
As seen in FIG. 46, the IEEE P1500 WSP 202 interface and architecture 4610 is separate from the IEEE 1149.1 TAP 318 interface and architecture 4604. Therefore the IEEE P1500 architecture is forced to include its own instruction register 314, its own set of selectable data registers 316, its own gating circuitry 308, and its own instruction 302 and data 304 control buses to WSP 202. The primary reason for this forced separation is due to the differences in operation between the TAP 318 and WSP 202 interfaces. The external test bus 4612 to WSP 202 is achieved using 9 signals (WSI, WSO, Clock, Capture, Shift, Update, Transfer, Select, and Reset). If circuit 4602 is a core, these 9 signals will be dedicated terminals of the core. However, if circuit 4602 is an IC, these 9 signals are not required to be dedicated ICs pins, as are the TAP pins 4608, and will typically be shared with functional pins on the IC and invoked only when testing of the IC is required. If they are shared it is not possible to use them for real time test, emulation, debug, or other operations that can be used with the TAP 318 and its dedicated test bus 4608. The non-dedicated nature of the WSP test bus 4612 will most likely limit use of IEEE P1500 in other areas such as emulation and debug. However, since improved testing of core based ICs is the primary objective of IEEE P1500 that limitation will not matter, especially since TAP based solutions already exist for these expanded needs.
If the circuit 4602 is a core for use in an IC it will require a 5 signal bus for interfacing to the TAP 318 and a 9 signal bus for interfacing to the WSP 212. The total number of signals therefore that need to be routed in the IC for connection to core 4602 is 14. In some ICs the routing of 14 test signals to a core can be prohibitive, especially if multiple cores exist with each potentially needing its own bus of 14 test signals. Thus having two separate standards implemented in a core, each with separate test bus interfaces, can lead to problems related to wire routing area overhead.
From the above description it is clear that if TAP based and WSP based domains are used in a circuit 4602, the area overhead will be increased due to the need of the WSP domain to have its own architecture separate from the TAP domain architecture. Also it is clear that access to WSP domains, unlike TAP domains, will be limited to testing circuits 4602 when circuits 4602 are in a non-functional mode of operation. Further, it is clear that due to the nature of the non-dedicated WSP 9 pin interface, the range of WSP interface support will be most likely limited to testing. Lastly, having both TAP and WSP based domains in cores can lead to IC wire routing and density problems.